| 摘要: |
| 为了提高频综的频谱纯度，提出了一种新型多级子谐波混频锁相环的设计方法,研制了一款超低相噪频综。介绍了该频综的设计方案，分析了关键技术，仿真和论证了相位噪声和杂散抑制等主要指标，最后对该频综进行了研制和实际测试。测试结果如下：工作频率为4 500~7 600 MHz，频率步进小于1 kHz，相位噪声优于-123 dBc/Hz@25 kHz，频率切换速度小于75 μs，杂散抑制大于70 dB，均满足设计要求，设计方案比较合理可行。采用该方法设计的频综具有小步进、低相噪、换频速度快、低杂散等特点，可用于高性能电子战接收机中，具有广阔的应用前景。 |
| 关键词: 电子战接收机 宽带频率合成器 C频段 多级子谐波混频 高纯度 |
| DOI： |
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| 基金项目:国防重点实验室基金（9140C130201150C13065） |
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| Design on a high spectral purity C-band frequency synthesizer |
| ZHOU Yehua,YE Baosheng,CHENG Ming,QIAN Huanyu |
| () |
| Abstract: |
| A novel multistage sub-harmonic frequency-mixing phase locked loop(PLL) is provided to improve frequency synthesizer′s spectral purity.Based on this method,an ultra- low phase noise frequency synthesizer is developed.The design of the frequency synthesizer is introduced and key technologies are analyzed .The main performance such as phase noise and spurious suppression is simulated and demonstrated.Finally,the C-band frequency synthesizer is measured.The synthesizer covers frequency from 4 500 MHz to 7 500 MHz with less 1 kHz step size .The measured phase noise at an output frequency of 7.49 GHz at 25 kHz offset is –123 dBc/Hz.Spurious does not exceed the 70 dB level and the switching time is less than 75 μs.The design scheme is more reasonable and feasible .With a small step size,fast frequency switching speed,low phase noise and low spurious characteristics,the synthesizer can be used in high performance electronic warfare receivers and has a broad application prospect. |
| Key words: warfare receiver wideband frequency synthesizer C-band multistage sub-harmonic frequency-mixing high spectral purity |
《电讯技术》编辑部 