| 基于嵌入式系统的误码仪的总体设计 |
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| 引用本文： | 古志强,石春和,贾盼恩.基于嵌入式系统的误码仪的总体设计[J].物流科技,2010,33(9):89-91. |
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| 作者姓名： | 古志强 石春和 贾盼恩 |
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| 作者单位： | 军械工程学院,河北,石家庄,050003 |
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| 摘 要： | 误码仪是专门为测试通信信道误码率而开发的仪器,其测试的直观性给工程实际应用带来了极大的便利。设计了基于嵌入式系统和FPGA的简易误码仪,充分利用了FPGA强大的可编程能力和丰富的资源,以及WinCE嵌入式系统体积小、功能强大等优势。设计了基于FPGA的误码测试板,该板通过PC104总线与PCM-3350嵌入式系统板进行通信,在实验平台上初步实现了其功能,具有很好的实用价值。
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| 关 键 词： | 嵌入式系统 误码测试仪 FPGA PC104 |
Design of BER Test Apparatus Based on Embeded System |
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| GU Zhi-qiang,SHI Chun-he,JIA Pan-en.Design of BER Test Apparatus Based on Embeded System[J].Logistics Management,2010,33(9):89-91. |
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| Authors: | GU Zhi-qiang SHI Chun-he JIA Pan-en |
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| Institution: | (Ordnance Engineering College,Shijiazhuang 050003,China) |
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| Abstract: | BER test apparatus is designed to test bit error rate of communication channel.Intuition of the test brings great conve-nience to the practical application.A sample BER test apparatus based on embedded system and FPGA is designed,making full use of the design flexibility and powerful function of FPGA and WinCE embedded system.The BER test board is designed and its communication with the PCM-3350 board depends on PC104.Its preliminary function is achieved on the experiment platform,It has a good practical value. |
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| Keywords: | FPGA PC104 |
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