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基于FPGA的专用信号处理器设计
引用本文:贾玉臣,吴嗣亮.基于FPGA的专用信号处理器设计[J].国际商务研究,2005,45(6):105-109.
作者姓名:贾玉臣  吴嗣亮
作者单位:北京理工大学信息科学技术学院电子工程系 北京100081
摘    要:用可编程门阵列(FPGA)实现了一个专用信号处理器,它以快速傅里叶变换(FFT)为核心工作单元,对四路零中频雷达回波依次进行去除直流分量、数据加窗、FFT、目标信号选大和相位参考信号检测等处理。各处理单元流水操作,保证了处理速度,提高了资源的利用效率。FFT算法为输入顺序输出位反序的D IT基2算法,采用递归结构实现,硬件共享设计节省了资源;同时,处理过程中采用块浮点算法,兼顾了定点的高速度与浮点的高精度;并对FFT结果进行了误差分析,给出了定点与块浮点两种算法时的均方误差上限。最后对整个设计进行了仿真验证,结果表明用FPGA实现专用信号处理器满足系统要求。

关 键 词:雷达设备  信号处理器  快速傅里叶变换  流水线  块浮点算法  设计
收稿时间:2004/10/11 0:00:00

Design of an FPGA-based Specific Signal Processor
JIA Yu-chen,WU Si-liang.Design of an FPGA-based Specific Signal Processor[J].International Business Research,2005,45(6):105-109.
Authors:JIA Yu-chen  WU Si-liang
Institution:Department of Electronic Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing 100081, China
Abstract:A specific signal processor is implemented whose core unit is FFT.Four-channel zero-IF radar echo is processed by it in the following order: removing DC component,data windowing,FFT,selecting the maximum object signal and detection of phase reference signals.All units work in pipeline style that guarantees a high processing speed and increases the usage efficiency of the resource.The FFT algorithm is DIT radix-2 with inputs in natural order and outputs in bit-reversed order and implemented with recursive architecture.The hardware share design saves resources.Meanwhile,block floating point algorithm is adopted in the processing which has the merits of high speed of fixed point and high accuracy of floating point.And the error of the FFT result is also analyzed.The upper bound of mean square error is given for the two algorithms of fixed and block floating point.Finally,the whole design is verified by simulation.The results show that implementation of the specific signal processor with FPGA meets system requirements.
Keywords:FPGA
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