| 基于锁相环的时钟相位插值电路设计与实现 |
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| 引用本文： | 段营,戎蒙恬,孙劲飞,诸悦.基于锁相环的时钟相位插值电路设计与实现[J].国际商务研究,2007,47(3):45-47. |
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| 作者姓名： | 段营 戎蒙恬 孙劲飞 诸悦 |
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| 作者单位： | 上海交通大学电子工程系,上海200240 |
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| 基金项目： | 国家自然科学基金
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上海市科委资助项目
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上海-应用材料研究与发展项目 |
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| 摘 要： | 千兆以太网收发器模拟前端的时钟恢复电路要求锁相环(PLL)能够提供"128相"等相位差的时钟信号.为了满足此要求,设计了一种相位插值电路,它在不增加四级VCO级数的基础上,对其输出时钟的相邻相位进行16插值.仿真结果表明,该插值电路使PLL的输出时钟相位从8相增加至128相,证明了电路的有效性.
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| 关 键 词： | 以太网 收发器 时钟恢复电路 锁相环 相位插值 压控振荡器 |
| 收稿时间： | 2006/7/19 0:00:00 |
| 修稿时间： | 2006/12/5 0:00:00 |
Design and Realization of a Clock Phase Interpolator Circuit Based on PLL |
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| DUAN Ying,RONG Meng-tian,SUN Jin-fei,ZHU Yue.Design and Realization of a Clock Phase Interpolator Circuit Based on PLL[J].International Business Research,2007,47(3):45-47. |
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| Authors: | DUAN Ying RONG Meng-tian SUN Jin-fei ZHU Yue |
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| Institution: | Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, China |
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| Abstract: | The timing recovery circuit in the analog part of 1000 Base -T Ethernet transceiver requires that the utilized PLL could provide 128 -phase clock signals within a single period. For meeting this demand, this paper presents a phase interpolator circuit which interpolates the two adjacent clock phases with a number of 16 while not changing the 4 levels of VCO. Simulation results show the effectiveness of this circuit which increases the output clock phases of the PLL from 8 to 128. |
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| Keywords: | ethernet transceiver timing recovery circuit PLL phase interpolator VCO |
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