一种频率合成器的建模优化与电路设计

根据数模混合集成电路系统级和行为级快速验证的需求，设计了一种卫星导航系统射频接收机前端的频率合成器。传统行为级模型一般是基于理想环路进行参数提取，误差较大。为此，首先，分别利用MATLAB和Verilog-AMS对频率合成器建立理想行为级模型与非理想行为级模型，并根据行为级模型提取与优化的环路参数，采用SMIC 180 nm CMOS工艺设计仿真电路级频率合成器；其次，建立MATLAB噪声模型，对电路级各个模块的噪声进行拟合，评估频率合成器系统的整体噪声性能。所提出的频率合成器设计方法对电路级设计具有前瞻性的指导，并有助于电路级的设计优化。

Model optimization and circuit design of a frequency synthesizer

According to the demand of fast verification of system level and behavioral level about digital-analog mix integrated circuits,a frequency synthesizer for the front end of the RF receiver used in Global Navigation Satellite System(GNSS) is designed. The traditional behavior level model is usually based on the ideal loop for parameter extraction with large error.To solve this problem,firstly,MATLAB and Verilog-AMS are used to establish ideal behavior model and non-ideal behavior model for frequency synthesizer respectively. According to the loop parameters extracted and optimized from the behavioral model,the circuit-level frequency synthesizer is designed and simulated based on SMIC 180 nm CMOS process. Secondly,the MATLAB noise model is established,and the noise of each circuit level module is fitted to evaluate the overall noise performance of the frequency synthesizer. The frequency synthesizer design method proposed has forward-looking guidance for circuit-level design and contributes to circuit-level design optimization.