| 超长可变点数FFT处理器设计与实现 |
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| 引用本文： | 高振斌,万红星,陈禾,韩月秋.超长可变点数FFT处理器设计与实现[J].国际商务研究,2005,45(4):92-96. |
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| 作者姓名： | 高振斌 万红星 陈禾 韩月秋 |
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| 作者单位： | 北京理工大学信息科学技术学院，北京理工大学信息科学技术学院，北京理工大学信息科学技术学院，北京理工大学信息科学技术学院 北京100081，河北工业大学信息学院，天津300130，北京100081，北京100081，北京100081 |
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| 摘 要： | 介绍了超长可变点数序列FFT处理器的实现方法。采取将一维大点数FFT转换为二维小点数子FFT处理的措施,减小了存储器规模。使用乒乓RAM将基本运算模块级联,形成流水线结构,可连续高速计算N点复数序列FFT/IFFT。用现场可编程门阵列(FPGA)实现了可计算1k~1M点序列长度可变的FFT/IFFT处理器。
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| 关 键 词： | 电子战接收机 超长可变点数序列 FFT/IFFT处理器 现场可编程门阵列 流水线结构 |
| 收稿时间： | 2004/10/22 0:00:00 |
An Ultra Long Point FFT Processor for Various-Size Data |
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| GAO Zhen-bin,WAN Hong-Xing,CHEN He,HAN Yue-qiu.An Ultra Long Point FFT Processor for Various-Size Data[J].International Business Research,2005,45(4):92-96. |
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| Authors: | GAO Zhen-bin WAN Hong-Xing CHEN He HAN Yue-qiu |
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| Abstract: | The implementation method of an ultra long point FFT processor for various size data is introduced. The FFT function can be split into two sub-transform-blocks, so the predicted gate count for the entire processor can be reduced significantly. Each sub-block consists of several identical butterfly computational elements, which are connected with ping-pong RAMs to reorder the data between the butterfly stages and to form a pipeline structure. A prototype of the processor is implemented by two FPGA chips, which can continuously perform any power-of-two-sized transform between 1k-point and 1M-point. |
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| Keywords: | EW receiver Ultra long point FFT/IFFT processor FPGA Pipeline architecture |
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