首页 | 本学科首页   官方微博 | 高级检索  
     检索      

正交信号发生器的FPGA设计与仿真
引用本文:雷能芳.正交信号发生器的FPGA设计与仿真[J].价值工程,2011,30(24):140-141.
作者姓名:雷能芳
作者单位:渭南师范学院,渭南,714000
基金项目:渭南师范学院重点科研计划项目
摘    要:正交信号发生器的FPGA实现通常都是基于查找表的方法,为了达到高精度要求,需要耗费大量的ROM资源去建立庞大的查找表。文中提出了一种基于流水线CORDIC算法的实现方案,可有效地节省FPGA的硬件资源。并根据DSP开发工具DSP Builder的优点,采用VHDL文本与Simulink模型图相结合的方法进行了FPGA设计,仿真结果验证了设计的正确性及可行性。

关 键 词:CORDIC算法  FPGA  DSPBuilder  正交信号

Design and Simulation of Orthogonai Signal Generator Based on FPGA
Lei Nengfang.Design and Simulation of Orthogonai Signal Generator Based on FPGA[J].Value Engineering,2011,30(24):140-141.
Authors:Lei Nengfang
Institution:Lei Nengfang (Weinan Teachers University,Weinan 714000,China)
Abstract:The common approach to implement orthogonal signal generator on FPGA is based on look-up tables,which require a huge volume of ROM to achieve high resolution.This paper proposes a pipelined architecture for implementation of orthogonal signal generator on FPGA,which,based on CORDIC algorithm,can save considerable hardware resources and improve the speed performance as well.According to advantages of DSP Builder,the system is designed by utilizing VHDL and Simulink module.The correctness and feasibility of this design is verified by simulation result.
Keywords:CORDIC algorithm  FPGA  DSP Builder  orthogonal signal
本文献已被 CNKI 维普 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号