基于FPGA的高速DUC设计与高效实现

提出了一种基于FPGA实现高速数字上变频（DUC）的方法。该方法采用一种新的多相内插滤波器的高效实现结构，利用多相内插滤波器中各分支滤波器间系数的特点，使多相内插滤波器消耗的乘法器数量减少一半；并采用一种并行结构的数控振荡器（NCO），可产生高数据率的上变频本振信号。利用该方法为某雷达中频回波模拟器设计了DUC模块，其输出数字中频信号的数据率可达1.2 Gsample/s，只消耗了少量资源，满足项目需求。

Design and efficient realization of high speed DUC based on FPGA

This paper proposes an access to the realization of high data rate digital up converter(DUC) based on FPGA. This method adopts a novel implementation structure of poly-phase interpolation filter and makes use of the characteristic of branch between filter coefficients to reduce the consumption of multiplier by half. Besides, the adoption of parallel processing Numerically-controlled Oscillator(NCO) can generate high data rate vibration signal. By following these methods, a DUC module is designed for a certain radar IF echo simulator, which can generate digital IF signal with data rate up to 1.2 Gsample/s. Few resources are consumed and the program needs are satisfied.