| S频段锁相频率合成器的设计 |
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| 引用本文： | 蒋涛,唐宗熙,张彪.S频段锁相频率合成器的设计[J].国际商务研究,2008,48(8). |
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| 作者姓名： | 蒋涛 唐宗熙 张彪 |
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| 作者单位： | 电子科技大学电子工程学院 |
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| 摘 要： | 介绍了小数式锁相频率合成器的设计方法及相关理论,分析了影响锁相环相位噪声的主要因素并设计了环路滤波器和Wilkinson功率分配器。由实验结果可知,小数式锁相频率合成器具有很好的相位噪声和较高的频率分辨率。
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| 关 键 词： | 频率合成器 锁相环 相位噪声 小数分频 |
Design of an S Band Phase Locked Loop Frequency Synthesizer |
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| JIANG Tao,TANG Zong-xi,ZHANG Biao.Design of an S Band Phase Locked Loop Frequency Synthesizer[J].International Business Research,2008,48(8). |
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| Authors: | JIANG Tao TANG Zong-xi ZHANG Biao |
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| Abstract: | The design method and correlated principles of fractional-N phase locked loop (PLL) frequency synthesizer are described. The factors that affect the phase noise are analyzed and the loop filter and the Wilkinson power divider are designed. The test result proves that the design has such advantages as good phase noise and high resolution. |
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| Keywords: | frequency synthesizer phase locked loop phase noise fractional-N |
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