| Viterbi译码器的优化设计 |
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| 引用本文： | 袁金仕,卢焕章. Viterbi译码器的优化设计[J]. 国际商务研究, 2005, 45(3): 159-161 |
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| 作者姓名： | 袁金仕 卢焕章 |
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| 作者单位： | 国防科技大学ATR实验室 湖南长沙410073(袁金仕)，国防科技大学ATR实验室 湖南长沙410073(卢焕章) |
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| 摘 要： | Viterbi译码算法用FPGA实现时，其硬件资源消耗与译码速度始终是相互制约的两个方面，通过合理安排ACS单元和路径度量存储单元可有效缓解这两方面的矛盾。本文以(2，1，6)卷积码为例，基于基4算法提出的动态路径度量存储管理方法能在不影响译码速度的前提下有效降低译码器的硬件复杂度。
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| 关 键 词： | Viterbi译码器 路径度量存储管理 |
Optimized Architectural Design of Viterbi Decoder |
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| YUAN Jin-shi,LU Huan-zhang. Optimized Architectural Design of Viterbi Decoder[J]. International Business Research, 2005, 45(3): 159-161 |
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| Authors: | YUAN Jin-shi LU Huan-zhang |
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| Abstract: | When Viterbi algorithm is implemented in FPGA, the occupation of hardware resource and the speed of decoder are two conflictive aspects. And it can be resolved by arranging ACS unit and path metric RAM reasonably. In the case of (2,1,6) code and based on radix-4 algorithm, a new dynamic management of path metric memory is introduced, which can deduce the decoder''s complexity effectively and improve the speed of Viterbi decoder relatively. |
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| Keywords: | ACS |
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