| 基于FPGA的多端口存储控制器设计 |
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| 引用本文： | 张阳,王中阳,王红胜,向凯全. 基于FPGA的多端口存储控制器设计[J]. 河北工业科技, 2010, 27(6): 401-405 |
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| 作者姓名： | 张阳 王中阳 王红胜 向凯全 |
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| 作者单位： | 军械工程学院计算机工程系,河北石家庄,050003;91053部队,山东青岛,266100 |
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| 摘 要： | 由于FPGA内部存储资源有限,通常需要使用外部扩展存储器,针对目前广泛应用的DDR2 SDRAM存储器,采用模块化方法设计了多端口存储控制器,详细介绍了控制器、仲裁器、译码器等关键模块的设计,并在开发板上进行了实现和测试,实验结果表明其有效带宽可达2.6 GB/s。
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| 关 键 词： | DDR2 SDRAM FPGA 存储控制器 仲裁器 译码器 |
Design of mult-i por t memory cont roller based on FPGA |
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| ZHANG Yang,WANG Zhong-yang,WANG Hong-sheng and XIANG Kai-quan. Design of mult-i por t memory cont roller based on FPGA[J]. Hebei Journal of Industrial Science & Technology, 2010, 27(6): 401-405 |
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| Authors: | ZHANG Yang WANG Zhong-yang WANG Hong-sheng XIANG Kai-quan |
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| Affiliation: | Department of Computer Engineering,Ordnance Engineering College,Shijiazhuang Hebei 050003,China;Troop 91053,Qingdao Shandong 266100,China;Department of Computer Engineering,Ordnance Engineering College,Shijiazhuang Hebei 050003,China;Department of Computer Engineering,Ordnance Engineering College,Shijiazhuang Hebei 050003,China |
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| Abstract: | Due to the internal storage limits of FPGA,it usually needs external storage.Aiming at the most widely used DDR2 SDRAM memory,a multi-port memory controller is designed by modular method.The key modules' implications are described in detail,including controller,arbiter and decoder.The design is implemented and tested in development board.The effective bandwidth reaches 2.6 GB/s as the results show. |
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| Keywords: | DDR2 SDRAM FPGA memory controller arbiter decoder |
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