| 一种快速全数字锁相环 |
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| 引用本文： | 曾黄麟. 一种快速全数字锁相环[J]. 国际商务研究, 1988, 0(5) |
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| 作者姓名： | 曾黄麟 |
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| 作者单位： | 四川轻化工学院电子工程系 |
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| 摘 要： | 本文根据突发式数字通信快速锁相要求,提出一种位同步信号提取的新的快速全数字锁相环方案.它比一般数字锁相环捕捉速度最大可以提高N/2倍,且环路的同步时间与量化相位误差的矛盾也得到了解决,因而环路精度也大有改善.本文主要以一阶环为例讨论位同步信号提取.
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| 关 键 词： | 通信 全数字锁相环 |
A fast all digital phase-locked loop |
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| Zeng Huang Lin. A fast all digital phase-locked loop[J]. International Business Research, 1988, 0(5) |
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| Authors: | Zeng Huang Lin |
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| Abstract: | This paper presents a new type of all digital phase-locked loop(ADPLL)used for extracting a bit-synchronous signal to meet the requirements of the fast phase-locked in burst digital communication.The fastest synchronous speed of the loop is increased N/2 than that of the general ADPLL.Phase error precision of the loop is improved largly with reducing contradiction of the synchronous time and phase quantized error. This paper discusses extraction of the bit-synchronous signal with a first-order ADPLL mainly. |
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| Keywords: | Communication All Digital Phase-Locked Loop |
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